1. Field of the Invention
The present invention is directed to a method and system for computing the database of R(f), L(f), and C matrices for lossy interconnects that are used as the basis for CAD tools evaluating wiring delay and crosstalk in various electronic circuits and systems.
2. Description of Prior Art
It has been shown in A. Deutsch, H. Smith, C. W. Surovic, G. V. Kopcsay, D. A. Webber, G. A. Katopis, W. D. Becker, P. W. Coteus, A. H. Dansky, G. A. Sai-Halasz, xe2x80x9cFrequency-dependent Crosstalk Modeling for On-chip Interconnectionsxe2x80x9d, Proceedings IEEE 7th Topical Meeting on Electrical Performance of Electronic Packaging, February, 1998, West Point, N.Y., pp. 35-38 that crosstalk evaluation on medium and long on-chip interconnections requires frequency-dependent R(f)L(f)C circuit representation. The traditional, lumped-circuit RC circuit underestimates crosstalk noise. A constant parameter RLC circuit will either under or over predict noise depending on line length and driver circuit size.
Typical examples of crosstalk noise predictions are shown in FIG. 1, where far-end (FEN) 3 and near-end (NEN) 4 crosstalk simulated with either FEN 1 or NEN 2 circuit topologies and using either distributed RC 5, RLC 6, 8, or R(f)L(f)C 7, 9 circuit representation are shown for 5-mm-long lines on layer M5.
Another example of crosstalk noise predictions is shown in FIG. 2, where simulated FEN 13, 14 and NEN 15, 16 crosstalk for ZDRV=Z0 and ZDRV=3Z0, are shown as a function of length for lines in layer M5. Both FIGS. 1 and 2 compare distributed RC, RLC, and R(f)L(f)C simulations.
The error in prediction can be in the range of 25-80% as tabulated in FIG. 3, which shows the results for both, FEN 31 and NEN 32 circuit topologies. In a FEN case 31, the noise is monitored at the far-end of the quiet line Q 33, which is farthest from the driving end on the active line A 34. The active and quiet lines have the drivers at the same near end. In the NEN case 32, the driver on 25 the quiet line 35 is at the far-end and the noise is monitored at the near end.
As shown in FIG. 4b, the error in the crosstalk prediction is caused by xe2x80x9cproximity effectxe2x80x9d around the signal conductors. Due to the sparse VDD and GND conductors available on chip, at high-frequency, current crowds around the conductors and the effective ground resistance R12 42 increases significantly.
The skin-effect, as seen from FIG. 4a, where R10 41 is shown to have very small rise with frequency, is not significant. The skin depth is
xcex4=1.0-1.5 xcexcm at +25xc2x0 C.
and
0.4-0.6 xcexcm at xe2x88x92160xc2x0 C.
As described in A. Deutsch, G. V. Kopcsay, V. A. Ranieri, J. K. Catald, E. A. Galligan, W. S. Graham, R. P. McGouey, S. L. Nunes, J. R. Paraszczak, J. J. Ritsko, R. J. Serino, D. Y. Shih, J. S. Wilszynski, xe2x80x9cHigh-speed propagation on lossy transmission linesxe2x80x9d, IBM Journal research and Develop., vol. 34, No. 4, pp.601-615, July 1990, the skin-effect would be fully developed if
xcex4xe2x89xa60.1t, where t is the conductor thickness.
In the example shown in FIGS. 4a, 4b, t=2.1 xcexcm. Due to the strong variation of R12 42 with frequency, the resultant current redistribution in the ground lines causes L12 44 to also show substantial variation. The L10 43 term, however, has very little decrease and thus the inductive coupling,
KL=L12/L11, where L11=L10+L12
will decrease with frequency. In the example shown, KL decreases from 0.65 to 0.41 for f=0.001 and f=10 GHz. KL is not constant as assumed in an RLC-circuit representation or zero as assumed in an RC case.
The signals propagated on long, critical interconnects, such as data buses between the CPU and the cache, have rise times of
tr=50-100 ps.
If these interconnects are viewed as low-pass filters having an xe2x80x9cupper-3dBxe2x80x9d frequency of
fc=xc2xdΠRC,
as explained in J. Millman, H. Taub, xe2x80x9cPulse, Digital, and Switching Waveformsxe2x80x9d, Chapter 2, pp.27-50, McGraw-Hill Book Co., NY, 1965, then
tr=0.35/fc, and fc=3.5-7.0 GHz.
The upper frequency range of interest is then 3.5-7 GHz, which is where most of the increase in R12 and decrease of L12 is shown. The slight increase in R10 and decrease of L10 will cause attenuation of the noise and variation in the series impedance of the line
Z(xcfx89)=R+jxcfx89L, where xcfx89=2Πf.
The variation in impedance affects the amplitude of the noise which travels in both directions on the quiet line, is reflected from the end devices, i.e., driver or receiver, and depends on the mismatch between ZDRV and Z(xcfx89).
All these affects are not captured by RC or RLC circuit and hence contribute to the errors shown in FIG. 3. In FIG. 4a, xcfx89L 45 is shown to exceed R10 41 for f greater than 0.8 GHz and therefore inductance has to be taken into account. This is why the RC circuit is in so much error. The RLC circuit assumes a constant KL and no attenuation. Only the R(f)L(f)C circuit is able to capture all the effects.
The R(f), L(f), and C matrices are used to synthesize a resection distributed circuit which represents the calculated frequency-dependent behavior of the series impedance Z(xcfx89) and shunt admittance Y(xcfx89)=jxcfx89C. FIGS. 5a, 5b show examples of calculated parameters R11=R10+R12 and R12 obtained from accurate three-dimensional calculations and predicted by the synthesized circuit. Very good agreement can be obtained. Such a distributed circuit using the subsection 53 shown in FIG. 5c is used in simulations to predict the crosstalk noise.
A technique for implementing this synthesis approach in a very efficient manner in a CAD tool is described in B. J. Rubin, S. Daijavad, xe2x80x9cCalculation of Mullti-Port Parameters of Electronic Packages Using a General Purpose Electromagnetic Codexe2x80x9d, Proceedings of the 2nd IEEE Topical Meeting on Electrical Performance of Electronic Packaging, EPEP""93, Oct. 20-22, 1993, Monterey, Calif., pp.37-39. FIG. 6 highlights the key parameters used to translate from the table to a fast simulator, which is part of the CAD tool, which relies on pre-calculated RLC matrices stored in large tables. These R(f), L(f), and C matrices are obtained from three-dimensional, 3D, calculations that are very lengthy.
One net topology, such as shown in FIG. 6, requires 40-60 hours of CPU time. A typical 7-layer on-chip wiring structure requires 31 such nets to be calculated and the database build up can take as long as two-and-a-half months. Any design or technology ground rule changes require a new set of calculations, thus lengthening the design cycle for bringing the microprocessor chip to market with subsequent significant loss of revenue.
The invention presents a technique for greatly reducing the time required for generating the large RLC look-up tables needed for the CAD tool that performs crosstalk violation checking on on-chip wiring. The technique relies on two-dimensional, 2D, or two-plus a fast three-dimensional 2D/3D, calculation of the circuit parameters. This allows a reduction of computation time from 40-60 hours to 20 minutes to 2 hours per net. The loss in accuracy is insignificant while the design productivity and product competitiveness is greatly increased.